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Integrated Infrastructure System for Simulation Tender - 137538994

The NATIONAL UNIVERSITY CORPORATION has issued a Tender notice for the procurement of a Integrated Infrastructure System for Simulation, Data, Learning, and Inference 1 Set in the Japan. This Tender notice was published on 11 Mar 2026 and is scheduled to close on 21 Apr 2026, with an estimated Tender value of Refer Document. Interested bidders can access detailed Tender information, eligibility criteria, and complete bidding documents by referencing TOT Ref No. 137538994, while the tender notice number is and Registering on the platform.

Procurement Summary

Country: Japan

Summary: Integrated Infrastructure System for Simulation, Data, Learning, and Inference 1 Set

Deadline: 21 Apr 2026

Posting Date: 11 Mar 2026

Other Information

Notice Type: Tender

TOT Ref.No.: 137538994

Document Ref. No.:

Competition: ICB

Financier: Self Financed

Purchaser Ownership: Public

Tender Value: Refer Document

Purchaser's Detail

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Tender Details

Integrated Infrastructure System for Simulation, Data, Learning, and Inference 1 Set
Classification :

0014 Office Machines & Automatic Data Processing Equipment

Summay of Notice :

⑴ Classification of the products to be procured : 14

⑵ Nature and quantity of the products to be purchased : Integrated Infrastructure System for Simulation, Data, Learning, and Inference 1 Set

⑶ Type of the procurement : Purchase

⑷ Basic requirements of the procurement :

A The system shall meet the following hardware requirements.

① The computing system shall consist of compute nodes composed of accelerator nodes equipped with computational accelerators and general-purpose CPU nodes.

② The total theoretical peak performance of the accelerator nodes (by double-precision floating-point arithmetic) shall be 140PFLOPS or higher. Emulation is also acceptable.

③ The total theoretical AI computation performance of the accelerator nodes (by FP4 or higher-precision floating-point arithmetic, without sparsity consideration) shall be 25EFLOPS or higher.

④ The total memory bandwidth of the accelerator nodes shall be 1.5PByte/sec or higher, and the total memory capacity shall be 200TByte or higher.

⑤ The CPUs of the general-purpose CPU nodes shall collectively provide 6, 000 or more cores. The theoretical peak performance (double-precision floating-point arithmetic) per core shall be 65GFLOPS or higher, memory capacity per core 2.0GByte or higher, and memory bandwidth per core 5.0GByte/sec or higher. The instruc...

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