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The COMMERCE, DEPARTMENT OF | NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY has issued a Tender notice for the procurement of a Chips Highthroughput Highresolution Xray Laminographytomography System for Advanced Packaged Semiconductor Devices and Substrates in the USA. This Tender notice was published on 25 Feb 2026 and is scheduled to close on 09 Mar 2026, with an estimated Tender value of Refer Document. Interested bidders can access detailed Tender information, eligibility criteria, and complete bidding documents by referencing TOT Ref No. 136554616, while the tender notice number is 1333ND26QNB030031 and Registering on the platform.
Procurement Summary
Country: USA
Summary: Chips Highthroughput Highresolution Xray Laminographytomography System for Advanced Packaged Semiconductor Devices and Substrates
Deadline: 09 Mar 2026
Posting Date: 25 Feb 2026
Other Information
Notice Type: Tender
TOT Ref.No.: 136554616
Document Ref. No.: 1333ND26QNB030031
Financier: Self Financed
Purchaser Ownership: Public
Tender Value: Refer Document
Purchaser's Detail
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Login to see detailsTender Details
Amendment 0001:
Amendment changes include the following:
The required response date is extended from February 26, 2026 to March 9, 2026
No Statement of work change
Questions and Answers:
Question1: Is there a cleanroom specification?
NIST Response: No. The instrument will be installed in a general purpose lab in the advanced measurement laboratory facility, but not within a cleanroom.
Question 2: Are you flexible on the footprint (size/dimension)
NIST Response: NIST expects the analytical instrument (source, stages, detectors, and shielded enclosure) to fit within the footprint specified by 10.2. Additional space is available in the lab around the instrument for service access, and for support equipment (including chase space for air compressor/dryer if required, and a work area in the lab for control and analysis PCs).
Question 3: Are the devices in JEDEC Trays?
NIST Response: Typically no. NIST requires significant flexibility to load samples that are within the size envelope described by specification 5. Samples will include full wafers, coupons (partial wafers), individual or groups of packaged devices, as well as atypical sample geometries. To meet requirement 5.1, vendors must include 5 sample carriers that are compatible with the automated loading system. Carriers supporting a JEDEC tray is only one possible way to meet that requirement.
See Combined Synopsis Solicitation_1333ND26QNB030031, Attachment 1 - Statement of Work, and Attachment 2 - Applicable Provisions and Clauses attachments for solicitation details.
Notice ID: 1333nd26qnb030031
Department/Ind. Agency: commerce, department of
Sub-tier: national institute of standards and technology
Office: dept of commerce nist
Product Service Code: 6640 - laboratory equipment and supplies
NAICS Code: 334413 - Semiconductor and Related Device Manufacturing
Inactive Dates: mar 24, 2026
Inactive Policy: 15 days after date offers due
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